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Show HN: E80: an 8-bit CPU in structural VHDL
I built a new 8-bit CPU in VHDL from scratch (starting from the ISA). I felt that most educational soft-cores hide too much behind abstraction, eg. if I can do a+b with a single assignment that calls an optimized arithmetic library, then why did I learn the ripple carry adder in the first place ? And why did I learn flip flops if I can do all my control logic with a simple PROCESS statement like I would with a programming language ? Of course abstraction is the main selling point of HDLs, but would it work if I tried to keep strictly structural and rely on ieee.std_logic_1164 only ?
Well, it did and it works nicely. No arithmetic libraries, no PROCESS except for the DFF component (obviously). Of course it's a bit of a "resource hog" compared to optimized cores, (eg. the RAM is build out of flip flops instead of a block ram that takes advantage of FPGA intermal memory) but you can actually trace every signal through the datapath as it happens.
I also build an assembler in C99 without external libraries (please be forgiving, my code is very primitive I think). I bundled Sci1 (Scintilla), GHDL and GTKWave into a single installer so you can write assembly and see the waveforms immediately without having to spend hours configuring simulators. Currently Windows only, but at some point I'll have to do it on Linux too. I tested it on the Tang Primer 25K and Cyclone IV, and I included my Gowin, Quartus and Vivado projects files. That should make easy to run on your FPGA.
Everything is under the GPL3.
(Edit: I did not use AI. Not was it a waste of time for the VHDL because my design is too novel -- but even for beta testing it would waste my time because those LLMs are too well trained for x86/ARM and my flag logic draws from 6502/6800 and even my ripple carry adder doesn't flip the carry bit in subtraction. Point is -- AI couldn't help. It only kept complaining that my assembler's C code wasn't up to 2026 standards)
16-bit address would have been good no? C64 > VIC2
From a pedagogical aspect, probably yes. A 16 bit address bus would allow me to make a difference between a word and an address which would improve understanding of a real CPU. On the other hand, allowing the word and the address to be interchangeable makes assembly a bit easier.
But the problem is that I'm using flip flops instead of a block RAM (see RAM.vhd, there's no PROCESS in it). As such I cannot take advantage of the internal FPGA ram. A 16bit address would be impossible to run on low cost FPGAs as it would require more than 500K flip flops.
Finally, 255 bytes (+1 for the input) is good enough for the purpose of understanding and running textbook excersises to it, I think.